Integrated circuits (ICs) are often required to drive a data bus quickly in order to meet various device and/or timing specifications. To meet these timing requirements, ICs are typically equipped with output drivers that have high signal switching strengths. FIG. 1 illustrates a computer circuit 10 that includes an output driver 20 and an input circuit 30. Output driver 20 may be a standard inverter stage that may be included within any type of IC driving device that transmits signals over a bus to any standard CMOS logic gate. Input circuit 30 may be a standard IC logic gate the presents a load capacitance (C.sub.L) to output driver 20. The magnitude of C.sub.L is determined by the combined capacitance of the elements included within input circuit 30. The magnitude of C.sub.L determines the amount of current that is needed in order to quickly drive input circuit 30 to an appropriate logic level (i.e., logic 0 or 1). Input circuit 30 must be driven at a frequency that is sufficient to meet timing specifications for the IC. Timing specifications for a particular IC may be set by a manufacturer or an end user.
The larger the magnitude of C.sub.L presented to output driver 20, the larger the amount of current that is necessary to drive input circuit 30 quickly to an appropriate logic level. In cases where the magnitude of C.sub.L is large, output driver 20 requires transistors with a strong current drive strength. Conversely, the smaller the magnitude of C.sub.L presented to output driver 20, the smaller the amount of current that is necessary to quickly drive input circuit 30 to an appropriate logic level. Transistors with low drive strengths, therefore, may be used in output driver 20. Consequently, if the magnitude of C.sub.L is known at the time output driver 20 is designed, a circuit designer may design the drive strength accordingly.
A problem may occur, however, if the magnitude of C.sub.L from input circuit 30 is not known. This situation may occur under circumstances in which output driver 20 and input circuit 30 are coupled together in computer circuit 10 by a manufacturer (or end user) who designed only one or neither of the components. If the magnitude of C.sub.L is relatively high as compared to the drive strength of output driver 20, output driver 20 may not be capable of driving input circuit 30 fast enough to meet the timing requirements of computer circuit 10. Therefore, the performance of computer circuit 10 may be diminished if C.sub.L of input circuit 30 is too high with respect to the drive strength of output driver 20.
Alternatively, if C.sub.L is relatively low, computer circuit 10 will operate at a high frequency due to the high current generated by output driver 20. The high frequency is caused by the current generated from output driver 20 that is in excess of that needed to drive input circuit 30. If computer circuit 10 operates at a high frequency, a problem with signal noise may occur. Accordingly, the potential noise problems caused by operating at high frequencies could diminish the performance of computer circuit 10.
FIG. 2 illustrates a common method for reducing high frequency noise. A fixed decoupling capacitor C 40 is added to computer circuit 10 in order to provide an additional capacitive load (i.e., in addition to C.sub.L). The additional capacitive load reduces the frequency of output driver 20 by storing excess charge in order to smooth out the noise of the signal. However, the addition of fixed capacitor 40 into an IC is not a very flexible approach.
Adding fixed capacitor 40 to computer circuit 10 after it has been constructed is generally cumbersome and impracticable. Also, in some circuits, C.sub.L is unknown making it difficult to accurately design fixed capacitor 40 for efficient system performance. For example, fixed capacitor 40 may provide an excessive load that will diminish circuit performance by slowing down the circuit in excess of what is needed. The designed capacitor may also be too small to provide an adequate load. In such a situation, either a second capacitor must be added, or the first capacitor must be removed and replaced with a larger capacitor. In either case, the proper decoupling capacitance that will maximize performance is likely to be found only through trial and error. Therefore, a flexible and efficient means for controlling the frequency between the interface of circuit elements is desired.